x86 Instruction Set Reference

MULSD

Multiply Scalar Double-Precision Floating-Point Values

Opcode Mnemonic Description
F2 0F 59 /r MULSD xmm1, xmm2/m64 Multiply the low double-precision floating-point value in xmm2/mem64 by low double-precision floating-point value in xmm1.
Description

Multiplies the low double-precision floating-point value in the source operand (second operand) by the low double-precision floating-point value in the destination operand (first operand), and stores the double-precision floating-point result in the destination operand. The source operand can be an XMM register or a 64-bit memory location. The destination operand is an XMM register. The high quadword of the destination operand remains unchanged. See Figure 11-4 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1 for an illustration of a scalar double-precision floating-point operation.

Operation
Destination[0..63] = Destination[0..63] * xmm2/m64[0..63];
//Destination[64..127] remains unchanged
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Protected Mode Exceptions
#GP(0)For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#GP(0)For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0)For an illegal address in the SS segment.
#PF(fault-code)For a page fault.
#NMIf TS in CR0 is set.
#XMIf an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UDIf an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.
Real-Address Mode Exceptions
#GP(0)If any part of the operand lies outside the effective address space from 0 to FFFFH.
#GP(0)If any part of the operand lies outside the effective address space from 0 to FFFFH.
#NMIf TS in CR0 is set.
#XMIf an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
Virtual-8086 Mode Exceptions
Same exceptions as in Real Address Mode
#PF(fault-code)For a page fault.
#PF(fault-code)For a page fault.
Instruction Latency Throughput Execution Unit
CPUID0F3n/0F2n0F3n/0F2n0F2n
MULSD xmm, xmm7/62/2FP_MUL